ASICs Versus Semi-Discrete Design
Application-specific ICs (ASICs) have the benefit of integrating a maximum amount of circuitry for a particular function on a single IC. This saves board space and cost. But designers beware. You could be "burned" by using an ASIC in your design.
The Appeal of ASICs
An example of a class of ASICs is PFC or PFC/PWM "combo" ICs, which contain essentially all the active control circuitry for power-factor correction and second-stage dc-dc conversion. Some PFC/PWM ICs, such as Micro Linear's ML4803, take integration and small size to the limit. The ML4803 is packaged in an 8-pin SOIC.
With these obvious benefits, it would seem that ASICs are the way to go, if the function you need has already been integrated. System-level design then becomes a simplified task of following the "typical circuit" in the part specifications, making minor adjustments for system specs, and voila! Board-level design has become easy and hot-shot designers will eventually all work for semiconductor companies.
Unfortunately, this scenario is fictional or at least highly idealized. A "just right" ASIC can be adjusted parametrically to the application while maintaining space and cost advantages. But the goal of commercial ASIC design is to make it as general as possible in its specificity. If the ASIC is optimized for one particular design, it is a custom IC, of little use for other applications. If it is too general, it is likely to be too suboptimal to be feasible.
In reducing package size and cost by reducing pin count, ASICs also reduce observability. In practice, a cheap ASIC will lure the unwary designer to adapt it to a somewhat different application than was intended. For instance, most PFC ASICs are based on a boost (common-active) converter topology. But what if you want to use a SEPIC instead? It has the advantage of eliminating power-on inrush current. The current-limit thermistor, a somewhat large and expensive part, can be eliminated. And though the SEPIC requires an extra winding, if the control circuitry is powered from a few turns on the boost power inductor, you already have a transformer. Besides, the SEPIC 1:1 transformer suggests use of a low-cost power-line common-mode filter inductor. So you try to adapt an ASIC to a SEPIC topology.
What happens? First, the small-signal (incremental) transfer function is different. For a boost, the cycle-averaged (low-frequency) transfer function is:
but for a SEPIC, it is:
Consequently, the ranges of voltages and currents changes, and parts values (such as sense resistors) that are found in control loops, change accordingly. But these value changes affect loop behavior.
The incremental control to input-current and control to output-current functions (though more difficult to derive) are also different in form (and the possible subject of a different article). This also affects the control scheme; poles and zeros appear in vastly different places (or not at all), and component values can become unfeasible to implement. Response times can become unacceptable. Additionally, ASIC control loops depend on a certain phase of input at their pins. Inversion requires additional circuitry.
Suppose you solve these problems only to find you cannot make spec because ASIC performance is too limited for your adaptation. More subtle difficulties involve layout. Because your topology is different, noise is higher at an ASIC pin, causing degraded performance. A short trace for a boost topology might be inescapably long for a SEPIC (or vice-versa). The ASIC is not designed to reject the higher noise, and you're sunk. Furthermore, your clever enhancement cannot be implemented using the ASIC because you cannot get inside it and make a change or two. ASICs do not always simplify design tasks. And they can be expensive because of their market-limited functions.
Another problem with ASICs is that they come and go. They are specific, and tend to have a short market life. While I was designing a PFC, I chose to use a Unitrode UCC3858. It had a nifty scheme for feedforward compensation of line-voltage variation using a DAC, which minimizes line ripple into the multiplier. While I was making progress on the design, TI acquired Unitrode and cancelled the part. Perhaps it was a good marketing decision for TI but not for my project. If I had used a well-established, multiple-sourced ASIC I would have avoided this problem, but no such ASICs for PFC were available. They were apparently too specific for that.
Because of these design limitations using ASICs, the creative designer tends to be pulled in the direction of design versatility. This leads to semi-discrete design – more parts than an ASIC but fewer than discrete transistors and MSI ICs. (MSI stands for medium-scale integration, such as op-amps, comparators, and dual flip-flops.) Though the trend is to flee from lower levels of integration, to consider maximum integration a high-priority design criterion can lead to the traps described previously. For low to medium-volume products not facing extreme space constraints, less integration can be optimal.
Semi-discrete design is based on the principle of using only well-established parts that are multi-sourced and enduring, such as the UC3842 PWM current controller, single-supply dual and quad op-amps and comparators (LM358, LM324, LM392, LM339), and a part such as a CA3080 for a multiplier. These parts are produced in high volume and have reached commodity price levels. The sum of their costs can be less than an ASIC. The disadvantage of additional board space is offset by more accessible nodes to probe in test, thus reducing production test cost. For development, such access is obviously desirable. Freed of ASIC constraints, novel benefits can be introduced, and the trade-off between parts count and performance better tailored to the application. For long product lifetimes, part obsolescence problems are minimized or avoided. Furthermore, semi-discrete designs become an "elastic" technology base from which adaptations can be pulled further for projects that differ from the base design. This saves redesign costs and reduces time-to-breakeven.
Sometimes design trends should not be taken for granted. They are not always best for every project. While integration is generally a good trend, it can also produce undesirable side-effects in development activities. Semi-discrete design is a concept that is worth keeping in mind, if not applying as a design approach when feasible.
ÓDennis L. Feucht, 2000