Amplifiers and logic gates are certainly different in function, and mathematically, analog entails continuous functions while digital functions are discrete. (Sampled-data systems are in-between; their samples of continuous quantities occur discretely in time.) Analog and digital appear to be quite different realms of technology. However, techniques of one often have analogous techniques in the other. Here, we take a look at some similarities.

The difference between analog and digital electronics diminishes with complexity. As digital approaches the functional complexity of computation, difference equations appear, and are comparable in the discrete domain to differential equations. DSP theory is more like analog electronics than logic design. At the register level, signal processing of discrete quantities is not unlike analog signal processing. To demonstrate the similarities, consider two technologies, op-amps and A/D converters (ADCs). While ADCs span the gap between analog and digital (and are not purely digital), they will serve to make the comparison.

Starting with the op-amp, it is more of an integrator than an amplifier in that its open-loop gain begins rolling off near 0 Hz, as shown below.

Now consider both integrating (dual-slope, D -S ) and parallel-feedback (successive-approximation (SA), tracking) type ADCs. The generalized parallel-feedback converter scheme is diagrammed below.

They also trade off speed for precision, with a plot similar to the op-amp, shown below.

As sampling rate increases, the number of digitized bits decreases. For both categories of ADCs, digital feedback of bits compares to the op-amp feedback. For instance, the SA converter makes one bit comparison per clock cycle. The sample rate consequently rolls off at a slope of –1 (–6 dB), as doubling the bits halves the sample rate for the same clock frequency. Integrating converters accumulate more counter bits, timing out a prolonged integration of their inputs, leading to more bits, but at the expense of time. Again, the log-log bits-speed slope is –1.

To increase converter speed, more processing is done in parallel. Instead of using a single comparator (which itself is a one-bit ADC), flash converters use 2^N  comparators to convert N bits of data simultaneously. This bandwidth-extension technique has an analog in analog: the f_T multiplier. The basic scheme is shown below.

To double bandwidth at the same gain, A, use two amplifiers with transconductance A/2 in parallel. Each amplifier, having half the gain of the original, has twice the bandwidth. And the current-summing at the output node does not decrease bandwidth, but allows the addition of the individual amplifier gains. Bandwidth can be further extended using three amplifiers (f_T-tripler), and more. But eventually, side-effects from paralleling cause diminishing returns. But the concept works for low parallelism, just as it does with comparators in flash converters. A typical implementation of the f_T-doubler as a differential amplifer is shown below.

A BJT implementation (omitting biasing circuitry) as a current amplifier is shown below.

The collector currents of the two diff-amp stages are connected in parallel, while their inputs are in series. Each diff-amp has a gain of A and an input of V_i/2. Then the total gain is:

where m = 2 for a doubler. The gain-bandwidth of each diff-amp is f_T (in the square brackets) multiplied by the leading m, for a gain-bandwidth of m× f_T. For a single diff-amp, with twice the input voltage (the right side of the above equation), the gain is the same but with a gain-bandwidth of only f_T. Parallelism has its advantages.

Finally, gain and precision can be traded off by cascading op-amps, as shown below.

Assume both op-amps have an open-loop gain of K and equal gain-bandwidths, f_T. The second amplifier stage is faster than the first because its closed-loop gain is less, as shown on the Bode plot (b), and it has a bandwidth of f_bw2. The cascaded combination has a gain-bandwidth that is no better than the individual amplifiers, but more loop gain is available at higher frequencies.

The digital analog - another ADC type - is the two-stage or half-flash ADC, sketched out as follows.

The two-stage ADC delivers n bits, or, for ADC1 = ADC2, 2× m bits. A same-speed, one-stage flash ADC of n bits has 2ⁿ comparators, while the above ADC has 2× 2^n/2 = 2^n/2 + 1. The two-stage ADC is less than half as fast but maintains the same precision of n bits with far fewer comparators.

While comparison with the cascaded op-amp in this case is not direct and simple, there are similarities. In an op-amp, more amplifier stages are required to achieve more gain just as more comparators are required in the full-flash ADC to achieve more bits of precision. In feedback amplifiers, more gain provides more precision. The reduction in comparators of the half-flash is greater than its speed reduction, thereby making its speed/comparator ratio (roughly analogous to gain-bandwidth product) better than the full flash. The cascaded op-amp similarly has no better speed than a single, closed-loop op-amp, but its precision at comparable speeds is better.

These three analog-digital comparisons underlay the message that the general principle of precision-speed trade-offs apply in both the analog and digital realms. Understanding their application in one realm prepares one to comprehend their application in the other, lesser-understood, realm.

Ó Dennis L. Feucht, 2000