One of the leading topics in line-operated power-converter design is to take power from the grid but not give any back. In other words, wall plugs should present to the ac source a resistive (and not a reactive) load. A power-factor corrector is the interface between the ac line and power converter that achieves this. So what is power-factor correction and why does it matter?

A power-factor controller (PFC) is a resistive load to the ac source. It provides a regulated dc output as input to an ordinary converter. Typical power supplies have as input a full-wave bridge rectifier followed by a storage capacitor. While the bridge diodes conduct, the line is driving an electrolytic capacitor – a nearly reactive load for the line. A reactive load causes line voltage and current to be out of phase, which is suboptimal for power distribution. Maximum power is delivered when they are in phase. The power factor is the cosine of the phase angle. A resistive load has a phase angle of zero and a PF of one.

Furthermore, instead of dissipating (that is, keeping) power, reactive loads store it and give some back later. This causes waveform distortion and harmonics on the ac line, defiling its purity. Line noise, surges, and dips reduce power quality. The developed world is now at the stage where "electrical environmentalism" is requiring clean treatment of the line from its users.

A PFC appears resistive to its source. This implies that the input current must differ from the sinusoidal source voltage by only a scaling factor. Their waveforms must be identical, though scaled by the effective input resistance of the PFC, by Ohm's Law.

How might one design such a circuit? If a converter, such as a boost (common-active) type were controlled so that its average per-cycle inductor current were commanded by a scaled input voltage (v_g scaled by T_g), the resulting current (i_g) would follow the voltage and the converter input would appear resistive. In other words, form a current control loop driven by the input sinewave. Because the loop would require a bipolar range to accommodate a sinusoid, introduce a bridge rectifier at the input. The rectified sinewave (sine magnitude), v_g, is now unipolar (assume positive-going with respect to PFC ground), but is not followed by a storage capacitor. That is placed at the output of the current-loop converter. What we have this far can be diagrammed as shown below.

As it stands, this PFC conceptual design provides no control over the dc output voltage. Coincidentally, the scale factor (or division ratio, if you imagine a voltage divider) for the sine magnitude input commanding current is free to be varied. If the scale-factor is electronically adjusted by using an analog multiplier, then a second outer control loop can be implemented to control the output voltage. Our scheme consequently works like this. The outer voltage loop compares the storage-capacitor output voltage, scaled by a voltage divider, H_V, against the commanded amount, set by a voltage reference. If too low, a voltage-loop error amplifier, A_Ve, increases its input to the multiplier. The other input is the sine magnitude (voltage-divided first by a fixed divider, T_g), which is increased in amplitude. The multiplier output now is a larger sine magnitude that commands the current of the current control loop. This loop compares the commanded current to the sensed converter input current. If the instantaneous value along the sine magnitude input current is too low, the current-loop error amplifier, A_Ce, output to the pulse-width modulator (PWM) increases, and the PWM duty-ratio, D, increases. This causes the active converter switch to be on longer, increasing the inductor current. This current dumps into the storage capacitor and the output voltage increases. The voltage loop responds accordingly. To summarize, the inner current loop is actually a switching transconductance amplifer with scaled sine magnitude input. It is also a programmable-gain amplifier (PGA), and the gain is servoed by a voltage control loop which adjusts average output current, i_o, to maintain output voltage, v_o.

The block diagram of the entire PFC is shown below.

The converter is represented by two blocks (transfer functions), the duty-ratio (or control) to source current, T_igd, and the source current, i_g, to output current, i_o, or T_igo. This diagram also shows the effect of the input voltage, v_g, on the converter, in that T_igd is a function of v_g. Current and voltage loop error (and dynamic compensation) amplifiers have gains of A_Ce and A_Ve respectively. R_s is the sense resistor (or equivalent) and H_e is the current-loop sampling effect. (This is the topic of another article.) H_V is the output voltage divider and Z_o is the storage capacitor and load – the next stage of power converter. T_c is the transfer function of the closed current loop, or

The feedforward path above T_g drives the divider input of the multiplier. As the line voltage varies, the peak to average ratio (p /2 @ 1.57) remains constant. Consequently, this variation can be compensated by dividing by the average. (The squaring function is also the topic of another article.) The amplitude is thus normalized to a constant value.

This is a PFC at the functional level of description. Design choices that follow include selection of converter type (usually a boost), compensation filters A_Ve and A_Ce (which are not trivial), and all the details of circuit-level design. What is important to do in design is to have the actual transfer functions of each of the above blocks. Then (and only then) is it possible to reasonably model PFC behavior. The derivations of the converter blocks are not trivial but have been worked out in the literature, using Richard Tymerski's switch model and Ray Ridley's current-loop sampling model.